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CMOS image sensor with focal plane SPIHT image compression

Zhiqiang Lin, University of Nebraska - Lincoln

Abstract

The wide spread use of today's digital camera and mobile camera phones drives the tremendous market growth for image sensors. This growth benefits from research and development progress on communication technology, sensor networks, electronic devices, and, especially, CMOS image sensors. The most important advantage of CMOS image sensors over CCD sensors is their ability to be integrated with other signal processing functions on a single chip, which enables small form factor, low cost, low power consumption, and high frame rate video on a single chip. Our research has focused on the parallel implementation of lossy image compression on the focal plane of CMOS image sensor. ^ Taking advantage of the parallel nature of image acquisition, we propose an alternative image decomposition method that exploits prediction via nearby pixels to replace the discrete wavelet transform decomposition used in the original Set Partitioning in Hierarchical Trees (SPIHT) image compression algorithm. The SPIHT coding algorithm is also modified to make it suitable for on-chip implementation and parallel processing. Our method achieves comparable compression performance with much lower computational complexity and allows image compression to be implemented directly on the sensor focal plane in a pixel and block parallel structure. The features of the proposed focal plane image compression scheme will benefit real-time, low rate and low power applications such as wireless video sensor networks and surveillance. ^ The test images from a fabricated sensor in 0.5μm technology show that the reconstruction Peak SNR (PSNR) performance of our focal plane prediction approach reaches more than 50dB, which is the highest performance reported. Also parasitic capacitance effect and charge injection noise in the prediction computational circuits are analyzed and discussed in detail. Subsequently, a CMOS image sensor with 49×57 pixel array is prototyped in 0.35μm CMOS technology to verify the compression scheme and circuit design. We present the design of each component on this sensor including the sensor array, in-pixel prediction computation circuitry, in-pixel ADC, digital correlated double sampling circuitry, transformed coefficient memory, and the SPHIT processor which operates in block-column parallel. The output from this CMOS image sensor is a compressed bitstream that can be used in progressive image transmission. ^

Subject Area

Engineering, Electronics and Electrical

Recommended Citation

Lin, Zhiqiang, "CMOS image sensor with focal plane SPIHT image compression" (2007). ETD collection for University of Nebraska - Lincoln. AAI3296996.
http://digitalcommons.unl.edu/dissertations/AAI3296996

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