Computer Science and Engineering, Department of


Date of this Version



S. C. Seth, B. B. Bhattacharya, and V. D. Agrawal,"An exact analysis for efficient computation of random- pattern testability in combinational circuits", Proc. 16th Int. Symposium on Fault Tolerant Computing (FTCS), 318-323, 1986.


© 1986 IEEE


Experimental evidence shows that low testability in a typical circuit is much more likely due to poor observability than poor controllability. Thus, from theoretical and practical standpoints, it is important to develop an accurate model for observability computation. One such model, in terms of supergates, is proposed in the first part of this paper thus complimenting our earlier work. It is now possible to obtain exact random-pattern testability for each line in a circuit.

The second part of the paper analyzes the supegate structure of a circuit from a graph theoretic viewpoint. Finding a supergate is related to determining the dominator tree in a modified circuit graph which provides an exact bound on the complexity of computation. The uniqueness of the cover extends to multiple output circuits, and the complexity of finding it is shown to be quadratic in the number of nodes in the circuit graph. By prior determination of the maximal supergate cover, unnecessary duplication in computation of testability values can be avoided.