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Built -in self -test design optimization for scan-based circuits
The move to deep-sub-micron processing technology and the increasing complexity of a single chip makes testability a key problem in VLSI design and scan insertion a broadly accepted solution in the industry. However, scan-based designs pose their own challenges to external testing via an automated test equipment (ATE) because of the ATE's limitations of memory depth, test channels and clock frequency. In this context, built-in self-test (BIST) design technique, with on-chip test generation and response analysis, becomes a viable alternative and is the focus of our work. For scan-based BIST designs, the most important parameters that must be optimized are fault coverage, test application time, area overhead, and power dissipation. Typically, an on-chip linear feedback shift register (LFSR) is employed for pseudo-random test pattern generation in BIST design. Although, with the LFSR it becomes possible to test the circuit with a large number of pseudo-random patterns, testing for random-pattern resistant faults can still take unacceptably long time. This dissertation presents a pseudo-random test compaction method to optimize test application time. Experimental results show that our method outperforms others in test length. Excessive amount of power is wasted during scan shifting in scan-based circuits. The proposed double-tree scan (DTS) architecture saves power by activating only [special characters omitted] scan flip-flops at each clock cycle, compared with O(f) for the traditional scan, where f is the total number of scan flip flops. The proposed DTS architecture with distributed control overcomes the clock-skew and routing problems associated with the centralized control. Usually, many pseudo-random test patterns generated by the LFSR may not contribute to fault coverage. Bypassing the LFSR states that produce these useless patterns can save up to 99% of total switching activity during scan shifting. The silicon area-overhead of this modification increases rapidly with the number of bypasses. We formulate and solve the area-overhead optimization problem as a consecutive test cover (CTC) problem, where the objective is to optimize a cost function combining the number of bypasses and the number of useful test patterns.
Zhang, Sheng, "Built -in self -test design optimization for scan-based circuits" (2006). ETD collection for University of Nebraska - Lincoln. AAI3236905.