Threaded MPI programming model for the Epiphany RISC array processor

Authors

David Richie, Brown Deer Technology, MD
James Ross, Engility Corporation, MD
Song Park, U.S. Army Research Laboratory, MD
Dale Shires, U.S. Army Research Laboratory, MD

Date of this Version

2015

Citation

Journal of Computational Science 9 (2015) 94–100

Abstract

The low-power Adapteva Epiphany RISC array processor offers high computational energy-efficiency and parallel scalability. However, extracting performance with a standard parallel programming model remains a great challenge. We present an effective programming model for the Epiphany architecture based on the Message Passing Interface (MPI) standard adapted for coprocessor offload. UsingMPIexploits the similarities between the Epiphany architecture and a networked parallel distributed cluster. Furthermore, our approach enables codes written with MPI to execute on the RISC array processor with little modification. We present experimental results for matrix–matrix multiplication using MPI and highlight the importance of fast inter-core data transfers. Using MPI we demonstrate an on-chip performance of 9.1 GFLOPS with an efficiency of 15.3 GFLOPS/W. Threaded MPI exhibits the highest performance reported for the Epiphany architecture using a standard parallel programming model.