A Novel Method to Improve the Test Efficiency of VLSI Tests

Authors

Hailong CuiFollow
Sharad C. Seth, University of Nebraska-LincolnFollow
Shashank K. Mehta, Indian Institute of Technology, KanpurFollow

Date of this Version

2002

Document Type

Article

Comments

Published in Proceedings of the 15th International Conference on VLSI Design (VLSID’02). Copyright 2002 IEEE. Used by permission.

Abstract

This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original sequence of test application. SEMATECH test data and simulation results are used throughout to illustrate the ideas.