Computer Science and Engineering, Department of
Date of this Version
1991
Abstract
Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. In this paper we suggest parallel versions of Larrabee’s algorithm, suitable for implementation on shared-memory and message-passing multicomputers.
Comments
Published in Proceedings, Fourth CSI/IEEE International Symposium on VLSI Design, 1991. doi: 10.1109/ISVD.1991.185095 Copyright 1991 IEEE. Used by permission.