Off-campus UNL users: To download campus access dissertations, please use the following link to log into our proxy server with your NU ID and password. When you are done browsing please remember to return to this page and log out.
Non-UNL users: Please talk to your librarian about requesting this dissertation through interlibrary loan.
Accurate computation of chip reject ratio based on fault latency
Abstract
The reject ratio is the fraction of defective chips that pass the acceptance test and, therefore, provides a simple and accurate measure of the tested product's quality. Although the assessment of quality is important, an accurate measurement of the reject ratio of tested chips is often not feasible. Statistical techniques for reject ratio prediction provide a possible way out of this dilemma but the available approaches are not accurate. They fail to realistically model the behavior of the process of testing. The detection of a fault by an input test vector is a random event. However, the detection of a fault in a sequential circuit requires a sequence of test vectors. This sequence activates the fault and propagates the effect of the fault to a primary output. Unlike a combinational circuit, many faults in a sequential circuit cannot be detected by a single vector. We propose a statistical model in which a fault is characterized by two parameters: a per-vector detection probability and an integer-valued latency. Irrespective of its detection probability, the fault cannot be detected by a vector sequence shorter than latency. A joint distribution of latency and detection probability over all faults is thus obtained. This distribution, characterized by actual test data, enables us to compute the reject ratio. The sensitivity of this approach to variations in the process parameters is also investigated. The concept of fault latency has further applications in test generation by fault sampling and in predicting test length to achieve a desired fault coverage.
Subject Area
Computer science|Electrical engineering
Recommended Citation
Das, Dharamvir, "Accurate computation of chip reject ratio based on fault latency" (1992). ETD collection for University of Nebraska-Lincoln. AAI9233396.
https://digitalcommons.unl.edu/dissertations/AAI9233396