Department of Physics and Astronomy: Publications and Other Research
Date of this Version
6-1-2000
Abstract
A trigger track processor is being designed for CDF Run 2. This processor identifies high momentum (PT > 1.5 GeV/c) charged tracks in the new central outer tracking chamber for the CDF I1 detector. The design of the track processor, called the extremely Fast Trackcr (XFT), is highly parallel and handle an input rate of 183 Gbitslsec and output rate of 44 Gbitdsec. The XFT is pipclined and reports the results for a new event every 132ns. The XFT uses threc stages, hit classification, segment finding, and segment linking. The pattem recognition algorithm for the three stages are implemented in Programmable Logic Devices (PLDs) which allow for in-situ modification of the algorithm at any time. Thc PLDs reside on three different types of modules. Prototypes of each of these modules have been designed and built, and are working. An overview of the hardware dcsign and the system architecture are prcsented.
Comments
Published by IEEE. IEEE Trans. Nucl. Sci. 47, 895 (2000). Permission to use. ©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.