Computer Science and Engineering, Department of


Date of this Version



Published in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN, VOL. CAD-3, NO. 2, APRIL 1984, pp. 123-126. Copyright 1984 IEEE. Used by Permission.


The results of production test on LSI wafers are analyzed to determine the parameters of the yield equation. Recognizing that a physical defect on a chip can produce several logical faults, the number of faults per defect is assumed to be a random variable with Poisson distribution. The analysis provides a relationship between the yield of the tested fraction of -the chip area and the cumulative fault coverage of test patterns. The parameters of the yield equation are estimated by fitting this relation to the measured yield versus fault coverage data.