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A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips. It is based on a model for the distribution of faults on a chip. The model requires two parameters, the average number (n0) of faults on a faulty chip and the yield (y) of good chips. It is assumed that the yield either is known or can be calculated from the available formulas. The other parameter, n0, is determined from an experimental procedure. Once the model is fully characterized, it allows calculation of the field reject rate as a function of the fault coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example.