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Detection of a fault in a sequential circuit requires a sequence of test vectors. This sequence activates the fault and propagates the effect of the fault to a primary output. To accomplish this, the test sequence must set flip-flops through a series of states. Unlike a combinational circuit, many faults in a sequential circuit cannot be detected by a single vector. We propose a statistical model in which. a fault is characterized by two parameters: a pervector detection probability and an integer-valued latency. Irrespective of its detection probability, the fault cannot be detected by a vector sequence shorter than the latency. A joint distribution of the latency and detection probability over all the failed chips is thus obtained. Using the new model, an analysis of chip failure data to predict actual yield and reject ratio is given. For a large-volume CMOS chip, tested by vectors having 99.7% fault coverage, this analysis gives a reject ratio of 43 parts per million that is believed to be in close agreement with the field data.