Computer Science and Engineering, Department of


Date of this Version



Published in Fourteenth International Conference on VLSI Design, 2001. doi: 10.1109/ICVD.2001.902659 Copyright 2001 IEEE. Used by permission.


The design of a finite state machine can be verified by simulating all its state transitions. Typically, state transitions involve many don’t care inputs that must be fully expanded for an exhaustive functional verification. However, by exploiting the knowledge about the design structure it is shown that only a few vectors from the fully expanded set suffice for both design verification and testing for manufacturing defects. The main contributions of the paper include a unified fault model for design errors and manufacturing faults and a function-based analysis of the circuit structure for the purpose of generating tests under the unified model. Experimental results on benchmark finite state machines are presented in support of this approach to test generation.