Computer Science and Engineering, Department of


Date of this Version



Published in Proceedings., Sixth Great Lakes Symposium on VLSI, 1996. doi: 10.1109/GLSV.1996.497635 Copyright 1996 IEEE. Used by permission.


The testability of a sequential circuit can be improved by controlling the clocks of individual storage elements during testing. We propose several clock control strategies derived from an analysis of the circuit, its S-graph structure, and its function. Through examples we show how the number of clocks affects the circuit’s testability. It is shown that if certain flip-flops (FFs) are scanned (or otherwise initialized), the remaining FFs can be controlled and initialized to any arbitrary state using the clock control. We derive a controllability graph and use it to assign clocks to FFs and to schedule the clocks to set the FFs to an arbitrary state during test. Our analysis of sequential benchmark circuits indicates that this could be an attractive scheme for combining partial scan with clock control.