Computer Science and Engineering, Department of


Date of this Version



Published in Proceedings, The Fifth International Conference on VLSI Design, 1992. Copyright 1992 IEEE. Used by permission.


This paper presents a switch-level test generation system for synchronous sequential circuits in which a new algorithm for switch-level test generation and an existing fault simulator are integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models all aspects of switch-level behavior. The time-frame based algorithm uses asynchronous processing within each clock phase to achieve stability in the circuit, and synchronous processing between clock phases to model the passage of time. Unlike earlier time-frame based test generators for general sequential circuits, the test generator presented uses the monotonicity of the logic network to speed up the search for a solution. Results on benchmark circuits show that the test generator outperforms an existing switch-level test generator both in time and space requirements.