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Design automation of RF CMOS low noise amplifiers

Gulin Tulunay, University of Nebraska - Lincoln


With the desire for high integration and low power consumption, the demands on the performance specifications of each radio-frequency (RF) functional building block are constantly increasing. Although RF blocks make up a small portion of the whole system, their design time and cost are relatively high compared to their analog and digital counterparts. In addition, as the operating frequency gets higher, the effects of parasitics make the design of RF blocks even more challenging. Low noise amplifiers (LNA) are one of the key performance bottlenecks in an RF system. They are required to contend with a variety of signals coming from the antenna. Most of the time the amplitude of the interferers are stronger than the desired signal, thus, low noise, high linearity and high gain LNAs are required. Computer-aided analysis and synthesis tools for RF are still in their infancy, and not used in industrial environments yet. Therefore, optimal solutions involving several design constraints are hard to achieve, and much of the effort is based on experience. A stand-alone design automation tool developed for the synthesis of RF complementary metal-oxide-semiconductor (CMOS) LNAs with arbitrary topologies is presented in this dissertation. To achieve this, LNA design is considered as an optimization problem with the performance specifications being put into the form of objective functions and constraints. Rather than relying on a commercially available circuit simulator such as Spectre or HSpice, the presented synthesis tool is complete with its own built-in modules for faster optimization. Foundry provided, silicon-verified RF device models are also incorporated into the synthesis procedure for accurate parasitic modeling. Agreement with simulation results makes the proposed synthesis tool an independent circuit design environment or an auxiliary tool that provides an initial design point for a commercial design environment such as Cadence, for shorter design times. To validate the proposed approach, an inductively source degenerated LNA circuit is first synthesized and then fabricated in a 0.25μm CMOS technology. The chip occupies a silicon area of 1:2mm x 1:4mm including the pads. Measurement results are presented which shows that a functional LNA can be obtained by using the proposed synthesis tool. It is anticipated that in addition to reducing the design time, this tool will also be helpful in exploring new LNA topologies that will meet the desired performance specifications.

Subject Area

Electrical engineering

Recommended Citation

Tulunay, Gulin, "Design automation of RF CMOS low noise amplifiers" (2007). ETD collection for University of Nebraska - Lincoln. AAI3273922.