Electrical & Computer Engineering, Department of
Date of this Version
Fall 12-2011
Abstract
The concept of introducing image processing logic within the spatial gaps of an array of photodiodes is the key factor behind the presented work. A two-dimensional massively parallel image processing paradigm based on 8X8 pixel neighborhood digital processors has been designed. A low complexity processor array architecture along with its instruction set has been designed and fully verified on a FPGA platform. Various image processing tests have been run on the FPGA platform to demonstrate the functionality of a design that uses 12 parallel processors. The test results indicate that the architecture is scalable to support high frame rates while allowing for flexible processing due to inherent programmability at a high level. The gate level logic synthesis results of the processor targeting a 0.13 μm CMOS technology indicates a low silicon area complexity, allowing for image sensor integration.
Adviser: Dr. Sina Balkir, Co-Adviser: Dr. Michael W. Hoffman
Included in
Electrical and Electronics Commons, VLSI and Circuits, Embedded and Hardware Systems Commons
Comments
A THESIS Presented to the Faculty of The Graduate College at the University of Nebraska In Partial Fulfilment of Requirements For the Degree of Master of Science, Major: Electrical Engineering Under the Supervision of Professors Dr. Sina Balkir and Dr. Michael W. Hoffman. Lincoln, Nebraska: December, 2011
Copyright (c) 2011 Anantha Krishna Nelliparthi