Electrical & Computer Engineering, Department of


Date of this Version



Daniel J. White, "Low-Power Analog Processing," Ph.D. dissertation, University of Nebraska-Lincoln, 2014


A DISSERTATION Presented to the Faculty of The Graduate College at the University of Nebraska In Partial Fulfillment of Requirements For the Degree of Doctor of Philosophy, Major: Electrical Engineering, Under the Supervision of Professor Michael Hoffman. Lincoln, Nebraska: November, 2014

Copyright (c) 2014 Daniel J. White


This dissertation presents the analog harmonic transform (AHT) and a first implementation in an integrated circuit. The transform is designed for a regular and simple hardware structure. It provides coefficients relating to an input signal's spectrum. These coefficients also have a simple relationship to the signal's Fouri\'er series coefficients.

The AHT is defined in its ideal form and evaluated for two example signal classification applications. Both military vehicle and bearing fault classification tasks are presented which validate the ability of a neural network to use the AHT coefficients to correctly classify the input signals. Because any real use of the AHT for classification would include various errors, a study determining the required hardware specifications is described.

These specifications are used to inform the design of a hardware implementation of the AHT coefficient generation. A prototype system in a 0.13um mixed-signal CMOS process was designed to confirm the new system's utility. The prototype chip included two separate blocks of AHT circuitry along with an on-board custom microprocessor to implement system control and supervision in a 4x4mm die area.

A new digitally-controlled operational transconductance amplifier (OTA) was designed as the core circuit element to support the AHT calculations. The OTA's offset and gain can be calibrated after fabrication to yield lower errors without significant increases in chip area or power consumption. This enables hardware implementation of applications, such as the AHT, which have strict offset requirements to maintain good system-level performance.

Testing of fabricated prototype chips confirms the ability of digital offset tuning to yield amplifiers having sub-10mV output-referred offset with both low power and small die area. An algorithm was created to adaptively find the optimum tuning code, needed because the tuning characteristic is not guaranteed monotonic. Testing also confirms the reliable operation of OTAs with extremely large (giga-ohm) output impedances. Low-frequency operation with long time constants requires these impedance levels to minimize integration capacitor size, the dominant factor in determining die area.

Adviser: Michael Hoffman