The Impact of Software and CAE Tools on SEU in Field Programmable Gate Arrays

Robert Katz, University of Nebraska - Lincoln
J. Wang, Actel Corporation, Sunnyvale, CA
J. McCollum, Actel Corporation, Sunnyvale, CA
B. Cronquist, Actel Corporation, Sunnyvale, CA

Document Type Article

Published in IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL 46, NO 6, DECEMBER 1999.

Abstract

Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements.