Seu Hardening of Field Programmable Gate Arrays (FPGAS) for Space Applications and Device Characterization

Robert Katz, University of Nebraska - Lincoln
R. Barto, INTELSAT, Palo Alto, CA
P. McKerrarcher, Johns Hopkins University/Applied Physics Laboratory, Laurel, MD
B. Carkhuff, Johns Hopkins University/Applied Physics Laboratory, Laurel, MD
R. Koga, The Aerospace Corporation, El Segundo, CA

Document Type Article

Published in IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 41, NO. 6, DECEMBER 1994.

Abstract

Field Programmable Gate Arrays (FPGAs) are being used in space applications because of attractive attributes: good density, moderate speed, low cost, and quick turn-around time. However, these devices are susceptible to Single Event Upsets (SEUs). An approach using triple modular redundancy m) and feedback was developed for flip-flop hardening in these devices. Test data showed excellent results for this circuit topology. Total dose and Single Event Effect (SEE) testing have been performed on recently released technologies. Failures are analyzed and test methodology is discussed.