Testability Analysis of Synchronous Sequential Circuits Based On Structural Data

Authors

Raghu V. Hudli, University of Nebraska-Lincoln
Sharad C. Seth, University of Nebraska-LincolnFollow

Date of this Version

1989

Comments

Published in Proceedings. Meeting the Tests of Time., International Test Conference, 1989. Copyright © 1989 IEEE. Used by permission. doi: 10.1109/TEST.1989.82320.

Abstract

Bounds on test sequence length can be used as a testability measure. We give a procedure to compute the upper bound on test sequence length for an arbitrary sequential circuit. We prove that the bound is exact for a certain class of circuits. Three design rules are specified to yield circuits with lower test sequence bounds.