Computer Science and Engineering, Department of
Computer Science, Computer Engineering, and Bioinformatics: Conference and Workshop Papers
Date of this Version
1993
Document Type
Article
Abstract
An implementation of a design for testability model for sequential circuits is presented. The flip-flops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complexity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are presented.
Comments
Published in Proceedings, Third Great Lakes Symposium on VLSI, 1993. 'Design Automation of High Performance VLSI Systems'. doi: 0.1109/GLSV.1993.224484 Copyright 1993 IEEE. Used by permission.