Clock Partitioning for Testability

Authors

Kent L. Einspahr, Concordia College, Seward, NEFollow
Sharad C. Seth, University of Nebraska-LincolnFollow
Vishwani D. Agrawal, AT&T Bell Laboratories, Murray Hill, NJ

Date of this Version

1993

Comments

Published in Proceedings, Third Great Lakes Symposium on VLSI, 1993. 'Design Automation of High Performance VLSI Systems'. doi: 0.1109/GLSV.1993.224484 Copyright 1993 IEEE. Used by permission.

Abstract

An implementation of a design for testability model for sequential circuits is presented. The flip-flops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complexity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are presented.