Computer Science and Engineering, Department of


Date of this Version



Published in ITC INTERNATIONAL TEST CONFERENCE, 2003, pp. 470-479. Copyright 2003 IEEE. Used by permission.


In a scan-based system with a large number of flip-flops, a major component of power is consumed during scan-shift and clocking operation in test mode. In this paper, a novel scan-path architecture called double-tree scan (DTS) is proposed that drastically reduces the scan-shift and clock activity during testing. The inherent combinatorial properties of double-tree structure are employed to design the scan architecture, clock gating logic, and a simple shift controller. The design is independent of the structure of the circuit-under-test (CUT) or its test set. It provides a significant reduction both in instantaneous and average power needed for clocking and scan-shifting. The architecture fits well to built-in self-test (BIST) scheme under random testing, as well as to deterministic test environment.