Low-Energy BIST Design for Scan-based Logic Circuits

Authors

Bhargab B. Bhattacharya, Indian Statistical Institute, Kolkata, IndiaFollow
Sharad C. Seth, University of Nebraska-LincolnFollow
Sheng Zhang, University of Nebraska-LincolnFollow

Date of this Version

2003

Comments

Published in Proceedings of the 16th International Conference on VLSI Design (VLSI’03). Copyright 2003 IEEE. Used by permission.

Abstract

In a random testing environment, a significant amount of energy is wasted in the LFSR and in the CUT by useless patterns that do not contribute to fault dropping. Another major source of energy drainage is the loss due to random switching activity in the CUT and in the scan path between applications of two successive vectors. In this work, a new built-in self-test (BIST) scheme for scan-based circuits is proposed for reducing such energy consumption. A mapping logic is designed which modifies the state transitions of the LFSR such that only the useful vectors are generated according to a desired sequence. Further, it reduces test application time without affecting fault coverage. Experimental results on ISCAS-89 benchmark circuits reveal a significant amount of energy savings in the LFSR during random testing.