MR-PIPA: An Integrated Multi-level RRAM (HfOx) based Processing-In-Pixel Accelerator

Authors

• Minhaz Abedin, SUNY Polytechnic Institute
• Arman Roohi, aroohi@unl.edu
• Maximilian Liehr, SUNY Polytechnic Institute
• Nathaniel Cady, SUNY Polytechnic Institute
• Shaahin Angizi, New Jersey Institute of Technology

Document Type

Article

Date of this Version

2022

Citation

DOI 10.1109/JXCDC.2022.3210509

Comments

Used by permission.

Abstract

This work paves the way to realize a processing-in-pixel accelerator based on a multi-level HfO_x RRAM as a flexible, energy-efficient, and high-performance solution for real-time and smart image processing at edge devices. The proposed design intrinsically implements and supports a coarse-grained convolution operation in low-bit-width neural networks leveraging a novel compute-pixel with non-volatile weight storage at the sensor side. Our evaluations show that such a design can remarkably reduce the power consumption of data conversion and transmission to an off-chip processor maintaining accuracy compared with the recent in-sensor computing designs. Our proposed design, namely MR-PIPA, achieves a frame rate of 1000 and efficiency of ~1.89 TOp/s/W, while it substantially reduces data conversion and transmission energy by ~84% compared to a baseline at the cost of minor accuracy degradation.