Generating Tests for Delay Faults in Nonscan Circuits

Authors

• Prathima Agrawal, AT&T Bell Laboratories
• Vishwani D. Agrawal, AT&T Bell Laboratories
• Sharad C. Seth, University of Nebraska-LincolnFollow

Document Type

Article

Date of this Version

1993

Comments

Published in IEEE DESIGN & TEST OF COMPUTERS 10(1):20-28, 1993. doi: 10.1109/54.199801 Copyright 1993 IEEE. Used by permission.

Abstract

This new method allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits. To test a given path, the authors augment the netlist model of the circuit with a logic block in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. The authors present results on benchmarks for nonscan and scan/hold modes of testing.