Computer Science and Engineering, Department of
Computer Science, Computer Engineering, and Bioinformatics: Conference and Workshop Papers
Date of this Version
2010
Document Type
Article
Abstract
The double-tree scan-path architecture, originally proposed for low test power, is adapted to simultaneously reduce the test application time and test data volume under external testing. Experimental results show significant performance improvements over other existing scan architectures.
Comments
Published in Proceedings, 23rd International Conference on VLSI Design, 2010, pp. 9-14. DOI 10.1109/VLSI.Design.2010.44 Copyright © 2010 IEEE. Used by permission.