A Unified Solution to Scan Test Volume, Time, and Power Minimization

Authors

Zhen Chen, Tsinghua University, BeijingFollow
Sharad C. Seth, University of Nebraska-LincolnFollow
Dong Xiang, Tsinghua University,Follow
Bhargab B. Bhattacharya, Indian Statistical Institute, Kolkata, IndiaFollow

Date of this Version

2010

Comments

Published in Proceedings, 23rd International Conference on VLSI Design, 2010, pp. 9-14. DOI 10.1109/VLSI.Design.2010.44 Copyright © 2010 IEEE. Used by permission.

Abstract

The double-tree scan-path architecture, originally proposed for low test power, is adapted to simultaneously reduce the test application time and test data volume under external testing. Experimental results show significant performance improvements over other existing scan architectures.