Empirical Computation of Reject Ratio in VLSI Testing

Authors

Shashank K. Mehta, University of Nebraska-LincolnFollow
Sharad C. Seth, University of Nebraska-LincolnFollow

Date of this Version

1999

Comments

In Proceedings of the Twelfth International Conference on VLSI Design, 1999. doi: 10.1109/ICVD.1999.745205 Copyright 1999 IEEE. Used by permission.

Abstract

Among significant components of testing cost are testlength, reject ratio, and lost-yield. In this paper a new approach is proposed to estimate the reject ratio. The empirical model is based on test-data properties that are believed to be invariant for a wide range of manufacturing technologies and types of tests. The analysis is carried out entirely in terms of the device test data, as might be available from wafer probe. Experimental results demonstrate robustness of the model.