Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects

Authors

Zhen Chen, Tsinghua National Laboratory for Information Science and Technology
Sharad C. Seth, University of Nebraska-LincolnFollow
Dong Xiang, Tsinghua University, Beijing
Bhargab B. Bhattacharya, Indian Statistical Institute, Kolkata, IndiaFollow

Date of this Version

2011

Citation

2011 Asian Test Symposium

DOI 10.1109/ATS.2011.61

Comments

© 2011 IEEE

Abstract

We present a combined hardware-software based approach to scan-chain diagnosis, when the outcome of a test may be affected by system faults occurring in the logic outside of the scan chain. For the hardware component we adopt the double-tree scan (DTS) chain architecture, which has previously been shown to be effective in reducing power, volume, and application time of tests for stuck-at and delay faults. We develop a version of flush test which can resolve a multiple fault in a DTS chain to a small number of suspect candidates. Further resolution to a unique multiple fault is enabled by the software component comprising of fault simulation and analysis of the response of the circuit to test patterns produced by ATPG. Experimental results on benchmark circuits show that near-perfect scan-chain diagnosis for multiple faults is possible even when a large number of random system faults are injected in the circuit.