Computer Science and Engineering, Department of


Date of this Version



European Design Automation Conference, 1992. EURO-VHDL '92, EURO-DAC '92. doi: 10.1109/EURDAC.1992.246252 Copyright 1992 IEEE. Used by permission.


This paper gives a method of finding all sensitizable paths in a non-scan synchronous sequential circuit. Path activation conditions of the circuit are mapped onto a single stuck type fault by adding a few modeling gates to the netlist. Only if the corresponding stuck type fault is found detectable by a sequential circuit test generator is the path considered sensitizable. A depth-first analysis of circuit topology, that determines all paths between primary inputs, primary outputs and flip-flops, employs a partial path hierarchy. Thus, all paths with a common unsensitizable segment need not be examined separately. Results on benchmark circuits show that ( I ) the number of sensitizable paths can be significantly smaller than that found by a static timing analyzer and (2) the partial path analysis adds to efficiency when the number of sensitizable paths is less than 20 percent.