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Test generation by fault sampling: A new approach for VLSI circuits
Abstract
In this dissertation we investigate the problem of test generation for VLSI circuits, and the concepts of testability analysis. The test generation problem for combinational circuits is known to NP-complete in the circuit size. Heuristics to solve this problem exist. The solution has two major costs associated with the test generation and fault simulation steps. For large sequential circuits the fault simulation costs are dominant. We introduce a new technique that reduces the fault simulation costs. Testability of a circuit used to guide the design and test process of a circuit. A new method of evaluating the testability of a circuit while performing test generation will be introduced. It has several advantages over other proposed methods for testability evaluation: (a) the evaluation effort is only incremental over standard test generation, (b) the results are applicable to random as well as deterministic test vectors, (c) the results are computed "on the fly" and refined continuously hence they can be used to provide useful feedback to the test generation process itself, and (d) the evaluation is independent of the circuit structure and hence applicable equally to sequential as well as combinational circuits. We will present experimental results about test generation and testability evaluation for benchmark circuits of up to several thousand logical gates.
Subject Area
Computer science
Recommended Citation
Farhat, Hassan A, "Test generation by fault sampling: A new approach for VLSI circuits" (1988). ETD collection for University of Nebraska-Lincoln. AAI8911109.
https://digitalcommons.unl.edu/dissertations/AAI8911109