Off-campus UNL users: To download campus access dissertations, please use the following link to log into our proxy server with your NU ID and password. When you are done browsing please remember to return to this page and log out.

Non-UNL users: Please talk to your librarian about requesting this dissertation through interlibrary loan.

Testability analysis and test generation for sequential VLSI circuits

Raghu Vishwanath Hudli, University of Nebraska - Lincoln

Abstract

Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem is NP-complete even for combinational circuits. As logic circuits become more dense, and more complex, the problem of test generation in general becomes computationally harder to solve. One accepted approach to reduce test generation difficulties is to consider testability as early as possible in the design cycle of the VLSI circuits. The dissertation proposes a testability measure based on the circuit structure. Structural analysis to predict the testability of a circuit is essential, since two circuits that are functionally equivalent, but structurally different, may require varying test generation efforts. It is shown that the test sequence length is a good testability measure. A graph theoretic approach is employed to compute the testability measure. The structure of loops in the circuit graph is an important factor that determines the testability of the circuit. The problem of finding a minimum set of nodes that will break all loops in a graph, commonly known as the feedback vertex problem is NP-complete. An algorithm based on heuristics is given to find small set of nodes that will break all loops. Design rules are given to reduce the test sequence length. Experimental results indicate the testability predictions are accurate. A temporal logic formalism is adopted to represent digital circuits. The temporal logic model is extended to enable causal reasoning. Temporal logic can model circuits hierarchically. A test generation algorithm based on the temporal logic model is proposed. The algorithm is a unified algorithm that works at multiple levels of descriptions of the circuits. The algorithm uses a set of heuristics to guide the test generation.

Subject Area

Computer science

Recommended Citation

Hudli, Raghu Vishwanath, "Testability analysis and test generation for sequential VLSI circuits" (1990). ETD collection for University of Nebraska-Lincoln. AAI9030126.
https://digitalcommons.unl.edu/dissertations/AAI9030126

Share

COinS