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Performance enhancement of bus-based parallel/distributed systems
Abstract
In a tightly coupled environment reusing slots in the traditional sense is not a lucrative option because each erasure node will introduce a few bits delay. For an on board system, where each slot is only a few bits long, such delay is intolerable. We have developed a method for reusing part of the bandwidth available from spatial/spectral bandwidth extension without introducing any buffering delay. Further, we have provided a polynomial time algorithm to optimally reconfigure the bus under the design constraints for any given traffic pattern. We have found that the reconfigured bus substantially outperforms the traditional slotted bus in most practical scenarios. In a dual-bus local area network the need for erasure nodes introduces a few bits of delay for each added erasure node, thus it is not profitable to make all nodes erasure nodes. This fact gives rise to the problem of placing a minimum number of erasure nodes on the network so that the throughput gain is maximum. This thesis gives the first polynomial time algorithm to solve the problem for all traffic conditions. The second part of the thesis considers partitioning and mapping task graphs for distributed shared memory systems (which includes bus based systems). The problem in its general form is known to be NP-complete and it is important to come up with simple but effective and fast heuristics. We have considered the tree task graphs which arise from many important programming techniques such as divide-and-conquer, branch-and-bound, etc. Further, we have proposed a polynomial time algorithm for data allocation in cacheless bus-based multiprocessor systems.
Subject Area
Computer science
Recommended Citation
Ray, Sibabrata, "Performance enhancement of bus-based parallel/distributed systems" (1995). ETD collection for University of Nebraska-Lincoln. AAI9538652.
https://digitalcommons.unl.edu/dissertations/AAI9538652