A Single-Chip Ultra-Wideband Based Wireless Sensor Network Node

Authors

Nathan R. Schemm, University of Nebraska at LincolnFollow

Date of this Version

Fall 10-28-2010

Document Type

Article

Comments

A DISSERTATION Presented to the Faculty of The Graduate College at the University of Nebraska In Partial Fulfilment of Requirements For the Degree of Doctor of Philosophy, Major: Engineering (Electrical Engineering), Under the Supervision of Professor Sina Balkır and Professor Michael W. Hoffman. Lincoln, Nebraska: December, 2010
Copyright 2010 Nathan R. Schemm.

Abstract

This dissertation presents the design of a next-generation wireless sensor network node. The node incorporates many new and innovative technologies such as an ultra-wideband radio which allows very low-energy communication, a low-power radiation detection front end, and an efficient implementation of dynamic voltage scaling which improves the energy efficiency of the integrated processor. The complete design is integrated on a single chip for maximum power savings and minimal size.

The ultra-wideband transceiver includes many novel techniques to produce a receiver with low power consumption and fast and accurate packet acquisition and reception. These include the use of a standard symmetric inductor in a non-standard way as a T-coil load which extends the bandwidth of RF amplifiers, and a novel baseband architecture which relies on parallel analog processing to achieve both low power and fast and accurate signal acquisition and tracking.

Other features include a very low power interface to radiation detection detectors which uses an architecture in which the ADC only samples when an event occurs. This decreases the power over a conventional continuous-sampling scheme. A low-power charge sensitive amplifier is designed for the front end while the peak detection is done in the analog domain before an ADC converts the peak value to digital.

An efficient implementation of dynamic voltage scaling allows for unmatched computational power consumption combined with good sleep mode power. This is achieved through the integration of two buck converters which have high efficiency even at light loads.

The complete design was integrated on a single chip using a 0.18 micron CMOS process with a total die area of 3x4.5 mm. The fabricated chip was tested and the measured results show that the chip does indeed achieve low power consumption. The measured results validate the approaches chosen, and field tests show the system is useful when interfaced to a variety of sensors for detecting various types of radiation.