A Low-Power, Low-Area 10-Bit SAR ADC with Length-Based Capacitive DAC

Authors

Zhili Pan, University of Nebraska-LincolnFollow

First Advisor

Sina Balkir

Second Advisor

Michael Hoffman

Date of this Version

Fall 12-2022

Document Type

Article

Citation

Z. Pan. A Low-Power, Low-Area 10-Bit SAR ADC With Length-Based Capacitive DAC. MS thesis, University of Nebraska-Lincoln, Lincoln, Nebraska, 2022.

Comments

A THESIS Presented to the Faculty of The Graduate College at the University of Nebraska In Partial Fulfillment of Requirements For the Degree of Master of Science, Major: Electrical Engineering, Under the Supervision of Professors Sina Balkir and Michael Hoffman. Lincoln, Nebraska: December, 2022

Copyright © 2022 Zhili Pan

Abstract

A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 µm^2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the second test chip for performance evaluation, and the test method is explained.

Adviser: Sina Balkir and Michael Hoffman