Design of a 1.8V 8-bit 500MSPS Folding-Interpolation CMOS A/D Converter with a Folder Averaging Technique

Authors

Dongjin Lee, Dongguk University
Jaewon Song, Dongguk University
Jongha Shin, Dongguk University
Sanghoon Hwang, Dongguk University
Minkyu Song, Dongguk UniversityFollow
Tad Wysocki, University of WollongongFollow

Date of this Version

2007

Comments

Published in 18th European Conference on Circuit Theory and Design, 2007. ECCTD 2007. 27-30 Aug. 2007; pages 356-359. ©2007 IEEE.

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500MSPS at 1.8V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.79mm² and it consumes about 200mW at 1.8V power supply. The DNL and INL are within ±0.6/±0.6LSB, respectively. The measured result of SNDR is 47.05dB.