Electrical & Computer Engineering, Department of
Date of this Version
2007
Abstract
A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12- b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.
Comments
Published in 18th European Conference on Circuit Theory and Design, 2007. ECCTD 2007. 27-30 Aug. 2007; pages 882-885. ©2007 IEEE.