Electrical & Computer Engineering, Department of


Date of this Version



Published in 18th European Conference on Circuit Theory and Design, 2007. ECCTD 2007. 27-30 Aug. 2007; pages 356-359. ©2007 IEEE.


In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500MSPS at 1.8V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.79mm2 and it consumes about 200mW at 1.8V power supply. The DNL and INL are within ±0.6/±0.6LSB, respectively. The measured result of SNDR is 47.05dB.