Design of Parity Testable Combinational Circuits

Authors

Bhargab B. Bhattacharya, Indian Statistical Institute, Calcutta, IndiaFollow
Sharad C. Seth, University of Nebraska-LincolnFollow

Date of this Version

1989

Comments

Published in IEEE TRANSACTIONS ON COMPUTERS, VOL. 38, NO. 11. NOVEMBER 1989, pp. 1580-1584. doi: 10.1109/12.42129 Copyright 1989 IEEE. Used by permission.

Abstract

The parity testability of a single output is related to its partition in terms of maximal supergates and then a scheme is proposed for making an untestable circuit parity testable by augmenting its maximal supergates. Only a small amount of extra logic and a single external test-mode pin is required to complete the design. The test procedure is simple and the hardware overhead is low.