An Experimental Study on Reject Ratio Prediction for VLSl Circuits: Kokomo Revisited

Authors

Dharam Vir Das, University of Nebraska-Lincoln
Sharad C. Seth, University of Nebraska-LincolnFollow
Paul T. Wagner, Delco Electronics, Kokomo, Indiana
John Anderson, Delco Electronics, Kokomo, Indiana
Vishwani Agrawal, ATBT Bell Laboratories, Murray Hill, New Jersey

Document Type

Article

Date of this Version

1990

Comments

Published in Proceedings, International Test Conference, 1990. Copyright © 1990 IEEE. Used by permission. doi: 10.1109/TEST.1990.114087.

Abstract

Assuring product quality is becoming increasingly more important for the semiconductor chip manufacturers. The reject ratio (defect level) provides a simple and accurate measure of a product's quality. However, measuring the reject ratio of tested chips is often not feasible or accurate. Statistical techniques for reject ratio prediction provide a possible way out of this dilemma. In this paper, we report on an experiment to verify the accuracy of reject ratio predictions by the available approaches. The data collection effort includes instrumenting the wafer probe test to obtain chip failures as a function of applied vectors and running a fault simulator to obtain the cumulative fault coverage of these vectors. The accuracy of reject ratio predictions is judged by assuming earlier stopping points for the wafer probe thereby gaining a measure of confidence In the final predicted value. The results of five different analysis are reported for over 70,000 tested die of a CMOS VLSl device manufactured at Deico.